Radiation tolerant electrostatic discharge protection networks

ABSTRACT

An ESD network. The ESD network including a redundant voltage clamping element in series with a first voltage clamping element between two voltage pads. The ESD network may be connected to a power voltage pad or a signal voltage pad either directly or through a dummy voltage pad. The voltage clamping elements may further comprise an array of unit cells wherein the array is electrically equivalent to single large transistors currently used in ESD networks. By creating an ESD network as an array of unit cells, benefits greater than those obtained by using a single transistor as a clamping or a trigger element are realized such as increased ballast resistance and less overall damage to the circuitry resulting from cosmic rays and particles.

RELATED APPLICATIONS

This application is a division of copending U.S. patent application Ser.No. 11/162,999 filed on Sep. 30, 2005.

FIELD OF THE INVENTION

This invention relates generally to the field of protection ofsemiconductor circuits from radiation effects, and in particular relatesto creating electrostatic discharge (ESD) circuits that are tolerant ofsingle event upsets.

BACKGROUND OF THE INVENTION

Semiconductor circuits are composed of a regular arrangement of atoms,usually silicon. In semiconductors, the arrangement of the atoms isoften in a lattice or mesh arrangement and the electrons and the holescreated by the lack of electrons are free to move within planes of thelattice. As semiconductor devices become smaller and smaller, fewer andfewer atoms are used to create an electronic device. Transistors ofsemiconductor materials often store sufficient charge to create digitalinformation by storing a 0 or a 1 state depending upon the thresholdvoltage of the transistor.

The primary component of nature is space and so there is mostly spacebetween the atoms in a semiconductor lattice. Also, as in all of nature,space is not quiet but rather active with high energetic particlesincluding heavy ions and cosmic rays from solar or galactic originsmoving about, colliding, transferring energy. These particles and/orrays collide with atoms in the semiconductor lattice and throughelastic, inelastic collisions, and/or field interactions between theenergetic particles and the atoms and/or electrons in the lattice, theatoms and/or electrons in the lattice may either change energy and/orposition such that the electronic state of the semiconductor device isno longer reliable. For instance, when the intruding particle is near ap-n junction, it may induce a soft error, or single-event upset becauseof the excess electron-hole pairs generated. If the electromagneticfield in the neighborhood of the p-n junction is sufficiently strong,the charged electrons and holes separate to a nearby device contact andwhen or if the collected charge exceeds a critical threshold value, arandom signal is registered. This is not an unusual occurrence. The VanAllen belt is a small region of high-energy particles held captive bythe magnetic influence of the Earth approximately 4000 miles or so abovethe Earth's surface. The Van Allen belt consists mainly of high-energyprotons, ten to fifty million electron volts (10-50 MeV), which areby-product of cosmic radiation. The probability of a nuclear hit betweenan energetic neutron interacting with a silicon large scale integrated(LSI) circuit is one out of 40,000 incident neutrons will interactwithin 10 microns of the circuit; further calculations reveal that atsea level almost every silicon-neutron hit within one micron of a LSIcircuit results in a soft error of single-event upset. During a quietsun period, the primary flux of particles averages seventy percentprotons and thirty percent neutrons, but during an active sun period thenumber of solar particles hitting the outer atmosphere increases amillion fold, and is larger than the flux of intergalactic cosmic rays.Thus, soft-errors or single event upsets are a real concern forsatellites and satellite-based communications and technology.

A single event upset (SEU) is defined by NASA as radiation-inducederrors in microelectronic circuits caused when charged particles loseenergy by ionizing the medium through which they pass, leaving behind awake of electron-hole pairs. SEUs are transient soft errors and arenon-destructive. A reset or rewriting of the device results in normaldevice behavior thereafter. SEUs typically appear as transient pulses inlogic or support circuitry, or as bit flips in memory cells orregisters. A multiple-bit SEU occurs when a single ion hits two or morebits causing simultaneous errors. Multiple-bit SEU is a problem forsingle-bit error detection and correction where it is impossible toassign bits within a word to different chips, such a dynamic randomaccess memories (DRAMs) and certain static random access memories(SRAMs). A severe SEU is the single-event functional interrupt in whichan SEU in the device=s control circuitry places the device into a testmode, halt, or undefined state.

A single event latchup (SEL) is a condition that causes loss of devicefunctionality because of a single-event induced current state. SELs arehard errors, and may cause permanent damage to the device. SEL resultsin a high operating current above the device specification and thelatched condition can destroy the device, drag down the bus voltage, ordamage the power supply. An SEL can be cleared by a power off-on resetor power strobing of the device, but if the power is not removedquickly, catastrophic failure may occur because of excessive heat, ormetallization or bond failure.

Single event burnout (SEB) is a more severe condition that causes devicedestruction because of high currents in a power transistor. SEBs includeburnout of power MOSFETs, gate rupture, frozen bits, and noise incharge-coupled devices. An SEB can be triggered in a power MOSFET biasedin the OFF state when a heavy ion passing through deposits enough chargeto turn the device on. SEBs can also occur in bipolar junctiontransistors.

The trend towards reducing device size and power; increasing the lineresolution, memory, and speed of electronic devices only heighten SEUsusceptibility. Integrated circuits already include electrostaticdischarge networks, the purpose of which is to dissipate any staticelectricity or other high voltage problems during manufacturing,construction, handling, shipping, etc. In space, however, ESD networksactually create problems and concerns, especially when the ESD networksare between the power rails, because of the shorting and physical damageas presented above when bombarded by particles and/or cosmic rays inspace. Bipolar circuits in electronic space applications have a highprobability of being hit by a cosmic ray and therefore require highreliability. This invention addresses the need to create reliable ESDnetworks for space applications.

SUMMARY OF THE INVENTION

These needs and others are satisfied by first realizing thatelectrostatic discharge networks pose a hazard to the integrity of thecircuitry in space. Upon that realization, then an electrostaticdischarge network has been invented, the network comprising: a triggerelement; a voltage clamping element connected to and initialized by thetrigger element; and a redundant element in series with the voltageclamping element in which the trigger element, the voltage clampingelement and the redundant element are located between a first voltagepad and a second voltage pad. The voltage clamping elements and/or theredundant elements may be a bipolar transistor, or a MOSFET transistor.There may also be a redundant trigger element either in series or inparallel with the first trigger element. Additional protection can berealized by connecting the ESD network to a dummy voltage pad or voltagerail not connected to processing circuitry.

In another embodiment of the invention, the clamping element further maycomprise an array of unit cells, each unit cell comprising at least onetransistor, the sum of the transistors of the array being electricallyequivalent to a single clamping element, each unit cell separated fromanother unit cell by a distance at least as great as the distance acolliding proton could displace in the network. There may be barriers ortrenches between the unit cells of the array.

A fault tolerant ESD network adapted to reduce the incidence of a systemfailure caused by a single event upset, comprises a first triggercircuit element; a first voltage clamp element connected to the firsttrigger circuit element; and a redundant voltage clamp element coupledin series with the first voltage clamp element. The first voltage clampelement and/or the redundant voltage clamp element and/or the triggerelement and/or a redundant trigger element may actually be an array ofunit cells, each unit cell comprising a plurality of transistors, theelectrical sum of the unit cells being electrically equivalent to asingle redundant voltage clamping transistor. Each unit cell may bedifferent than another unit cell in the array.

The invention is also considered a method to design an ESD protectionnetwork, comprising the steps of: defining a reliability requirement ofan integrated circuit for a single event upset; defining anelectrostatic discharge requirement using a technology database file andESD data; defining circuit topology of a redundant ESD element in serieswith a voltage clamping element of the ESD protection network to beapplied between a first voltage and a second voltage; defining a unitcell to comprise the redundant ESD element using a SEU tool; andevaluating the probability of failure of the ESD protection network.

The invention is also a method to protect electronic circuitry in space,by first realizing that electrostatic discharge networks can causecircuitry to experience single event upsets or worse in space, and thenincluding a redundant voltage clamping element in series with a firstvoltage clamping element between two voltage pads in the electrostaticdischarge networks; and connecting at least one trigger element to theredundant voltage clamping element and the first voltage clampingelement. The advantages of the invention set forth will further berealized upon a careful reading of the Description of the Invention inconjunction with the included Drawing.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is an electrical schematic of a prior art power clamp used incircuits.

FIG. 2 is an electrical schematic of a prior art ESD power clamp.

FIG. 3 is an electrical schematic of an ESD power clamp having an SEUredundant element in accordance with an embodiment of the invention.

FIG. 4 is an electrical schematic of an ESD power clamp with radiationtolerant redundant elements in series in accordance with an embodimentof the invention.

FIG. 5 is an electrical schematic of an ESD power clamp with radiationtolerant redundant elements in parallel in accordance with an embodimentof the invention.

FIG. 6 is an electrical schematic of a radiation tolerant power clampused with an isolation bus in accordance with an embodiment of theinvention.

FIG. 7 is a pictorial representation of an array of ESD cells inaccordance with an embodiment of the invention.

FIGS. 8 a-8 d are pictorial representations of different unit cells ofan ESD array in accordance with different embodiments of the invention.

FIG. 9 is a simplified flow chart of the method by which an ESD arraycan be designed in accordance with an embodiment of the invention.

DETAILED DESCRIPTION OF THE INVENTION

As discussed earlier, the collision of heavy ion particles often leadsto secondary breakdown events in space caused by high energy protons andneutrons colliding with the silicon lattice of electronic circuitsleading to fission fragments and damage to the electronic devices.Electrostatic discharge networks (ESD) can be used to quickly removepower from a circuit resulting from bombardment by cosmic rays but whenthe ESD network itself is hit, then catastrophic failure may occurbecause of excessive heat, or metallization or bond failure.Bipolar-based ESD networks, moreover, actually fail in spaceapplications. Hereinafter the distinction between SEUs, SELs, and SEBsshall be merged and the event, whether it be a latch-up or a burn-out,shall simply be referred to a single event upset (SEU). Until now, thefailure of ESD networks in space from SEUs has not been addressed.

FIG. 1 is a schematic of a prior art silicon germanium power clamp 100that limits the current in an electrostatic discharge network. The powervoltage, Vdd, 110 is connected across a trigger device 120 and a clampdevice 130. The emitter of the trigger device 120 is connected to thebase of the clamp device 130. A bias resistor 126 connected to theemitter of the trigger device limits the current flow to ground or Vss150. In parallel to the bias resistor 126 is a ballast resistor 136connected to the emitter of the clamp device. The ballast resistor 136redistributes current through the clamp to provide electrical andthermal stability. FIG. 1 also shows a proton 160 colliding with asilicon atom 170 in the base of the clamping device 130. As a result ofthe collision, several events can occur. First, there can beelectron-hole pair generation in the area of the collision; and second,the proton may be deflected and the silicon atom may recoil; and in somecircumstances, the silicon atom may be fragmented causing permanentdamage in the lattice leading to electrical and mechanical failure ofthe circuit. The mechanical and electrical damage can occur in a baseregion of a bipolar transistor creating an electrical short, called asilicon bipolar pipe, between the emitter and collector leading to thetransistor failure. When this failure occurs in electrostatic dischargenetworks themselves, additional problems can arise because the entirechip or circuitry is no longer protected.

FIG. 2 is a schematic of a prior art standard ESD power clamp 200. Thetop of the circuit is connected to an operating voltage Vdd 110. Thereis a trigger element 120 whose emitter is connected to a bias resistor126 and the base of a clamping device 130. In addition, the emitter ofthe trigger element 120 is also connected to a number of other clampingelements 230, 232. Each clamping element 130, 230, 232 has its ownballast resistor 136, 236, 238, respectively. Note that each clampingelement is still connected between Vdd 110 and Vss 150, such that a SEUcould still disrupt the function of the circuit.

An ESD network having redundant elements can be used in a variety ofsemiconductor technologies, typically of silicon but also any TypeIII/V, Type II/IV semiconductor combinations, including but not limitedto gallium arsenide, silicon germanium, indium phosphide,silicon-germanium-carbon, silicon-on-insulator, silicon bipolar etc. Infact, it is also realized that such an ESD network with a redundantelement as described herein is applicable to an ESD network of MOSFETtransistors because they inherently have a parasitic silicon bipolartransistor. SEUs are particularly problematic with bipolar transistors,and homo- and heterojunction transistors because these transistors havenarrow regions that make it easy for the collector to short with theVdd, or the emitter to short to ground.

One embodiment of a radiation tolerant ESD network has an ESD redundantcircuit element in series or in parallel with the trigger element.Consider the simplified circuit diagram of FIG. 3. A redundant circuitelement 330 may be connected to the same or different trigger element120. A trigger element 120, which could also be the same or differenttrigger element as above, is also connected to the clamp device 130.Note that the redundant circuit element 330 is connected across a pad.For example, in FIG. 3, the pad is a power supply rail, voltage Vdd 110,and is connected through the circuits to another power supply rail orground, Vss 150. The pad may also be a signal pad, wherein the ESDnetwork as described herein is connected to an input signal pad, such asan input/output signal pad and the remaining circuitry. The inventor hasdiscerned that redundant element 330 reduces and can even eliminate theprobability of a SEU-induced electrical short in ESD networks bydecoupling the voltage clamp element 130 from the voltage pad 110. TheSEU redundant element 330 may be connected in series or parallel withthe trigger element; but the SEU redundant element 330 is preferablyconnected in series with its respective clamping element. There may bemore than one SEU redundant element connected in parallel with otherredundant elements such that voltage clamping values sum together; justas there may be more than one clamping element in parallel with otherclamping elements. One of skill in the art will further appreciate thatthe use of the word “redundant” does not necessarily mean identical,although the redundant element could be identical to either or both thetrigger element and/or its respective clamping element. The redundantaspect of the element refers to its function, i.e., the redundantelement 330 must fulfill some minimum limit or objective. When theredundant element 330 is used for ESD protection, it must have a netbreakdown voltage greater that the voltage from the pad, e.g., Vdd 110or the signal voltage. In other words, for ESD protection, the sum ofthe breakdown voltages across the redundant element 330 and the triggerelement 120 or clamping element 130 independently must be greater thanthe application voltage.

FIG. 4 is a simplified circuit diagram of a radiation tolerant ESDnetwork 400 having redundant elements 410, 330, 430, 440. Redundantelement 410 may be a trigger element as a first stage, with clampingelements 330, 430, 440 as a second stage.

Similarly, trigger element 120 would also be considered a first stage,with clamping elements 130, 432, 442 as a second stage. The redundantsecond stage is in a series cascode arrangement with the clamping secondstage, i.e., each redundant element is in series with a voltage clampingelement between the pad, power voltage Vdd 110, and its respectiveclamping element 130, 432, 442. Redundant trigger element 410 isconnected to the second stage SEU redundant elements 330, 430, 440. Inthis embodiment, the redundant trigger element 410 is parallel to thetrigger element 120 for the clamping elements 130, 432, 442. In somecircumstances, it is desirable to bias the SEU redundant element, forexample, the redundant trigger element 410 can be grounded with resistor412. Clamping elements 130, 432, 442 may have substantially the same ormay have different voltage clamping capabilities from each other andfrom their respective redundant elements 330, 430, 440.

FIG. 5 is a simplified circuit diagram of another embodiment of aradiation tolerant ESD circuit 500 in which the first stage, theredundant trigger element 510, is connected in series to the other firststage, the trigger element 120. The second stage comprising redundantclamping elements 330, 430, 440 is also in series with its respectiveredundant second stage, clamping elements 130, 432, 442.

Whether the radiation tolerant ESD circuit is shown as in FIG. 4 or inFIG. 5, the power or signal voltage pad Vdd 110 may yet be furtherisolated from the ESD power clamp circuit 500 using a redundant dummypad 610, such as shown in FIG. 6. Between the power or signal voltagepad 110 and the dummy pad 610 there may be a current limit circuit 620for the input/output chip circuitry 644; and another current limitcircuit 630 between the power or signal pad 110 and the dummy pad 610for the core circuitry 650. The ESD power clamp circuit 500 could be inparallel to the core 650; or could be in parallel with the both the core650 and the current limit circuit 630. Note that in FIG. 6, two ESDprotection networks 642 and 500 are shown; these networks may be thesame or different depending upon their function. ESD protection network500 is intended to protect the core 650 from ESD damage; whereas ESDprotection network 642 may protect the I/O processing 644.

With respect to FIG. 7, the impact of an SEU can be even further reducedby creating each redundant and/or clamping element or trigger element asan ESD array 700 of small cells 710, 720. In the previous embodiments,one clamping element, one redundant element, or one trigger element weredisplayed. Typically, electrostatic discharge networks have largetransistors on the order of fifty to hundreds of microns long. In afurther embodiment, when a plurality of transistors of a smaller size,e.g., one micron, form a cell and the cells form an array that replaceone large 100 or 1000 micron transistor, additional SEU resistance isachieved in ESD networks. This embodiment is particularly advantageousfor bipolar transistors.

The advantages of such an array 700 replacing each trigger, clamping,and/or redundant element is that the charge collected by each transistoris less, the probability of a single transistor experiencing ancollision is less, and the increase in resistance is greater; theseadvantageous factors combine to reduce the probability of a SEU event(σ(π,Σl), σ(ν,Σl) event) in an ESD network. The self-ballasting effectof the array 700, moreover, protects more than merely adding redundancyand further limits the current of a given element if a SEU-inducedfailure occurs. The ESD array 700 further allows customization andpersonalization for the space environment, and parts per million (PPM)reliability requirement of space application and ESD requirements. TheESD circuit still has the requisite resistance but it is digitated intoa plurality of resistances to decrease the probability of being hit andcreating a natural series resistance that does not draw as much currentas a large single transistor.

An ESD array 700 contains a plurality of unit cells 710, 720. The sizeof and the distance between the unit cells 710, 720 affect theprobability of failure of more than one unit cell. The distance betweenthe unit cells is preferably larger than the range of particledistribution and the length of track of the particles. For example, analpha particle may travel up to 80 microns, so it is preferred that thedistance be on the order of or greater than 80 microns.

The size of the unit cell is actually dependent upon many considerationsas will be discussed with respect to FIG. 9. In general, however, theESD networks of FIGS. 4-6 may be hundreds or thousands of microns. Inorder to be electrically equivalent, then the number of unit cells maybe on the order of tens or hundreds of unit cells. For example, if apower clamp transistor is on the order of 1000 microns wide and has aseries resistance of one ohm, the electrical equivalence might be tenunit cells of 100 microns each or there may be 100 units cells of 10ohms per cell or there may be 1000 unit cells of one ohm each. Thenumber, width, and resistance of the unit cell may vary withapplications. The transistors may be of any electrical arrangementwithin the unit cell that supplies the equivalent protection as a singleclamping or trigger or redundant element.

FIGS. 8 a through 8 d are simplified representations of a variety ofunit cells 800. In FIG. 8 a, between the unit cells 710, 720 are aplurality of other circuit elements R1 802, R2 804, R3 806 that may bepart of or separate from the ESD circuits. The ESD array may furtherinclude SEU prevention features such as multiple high or mediumbreakdown or high performance heterojunction transistors, any of whichmay be characterized by speed and/or have a different base width. OtherSEU prevention features may include ballasting resistors, and/or chargebarriers such as trenches, guard rings, N-wells. The ESD gate array mayfurther include process structures, such as heavily doped buried layerconnecting implants, reach-throughs, and/or buried grids. A trench is anactual trough between the unit cells of the ESD array. FIGS. 8 b and 8 cshow a unit cell 810 having deep trenches 812, 814 on either side of thebipolar transistors 710, 720. In FIG. 8 b, trench 814 separates thetransistors 710, 720 from the circuit elements R2 804, R1 802, and R3806. In FIG. 8 c, the circuit elements R2 804, R1 802, and R3 806 arecontained between the trenches 812, 814. A trench may be of sufficientdimensions to prevent charge from entering the unit cell, such as 3-12microns deep and 1 micron wide; a trench may partially or completelysurround the unit cell 830 in a circular, rectangular, or othergeometric arrangement. FIG. 8 d is an illustration of a unit cell 830having both trenches 812, 814 and a charge barrier 832. Examples ofcharge barriers include diffusions of N-wells or substrate contacts, orother devices that college charge. An example of a diffusion of N-wellsmay be arsenide or phosphorus at a concentration of 5×10¹³ atoms percm³. Use of both the trenches 812, 814 and the guard ring 832 provideadditional protection from SEUs.

FIG. 9 is a simplified flow chart of a process by which an ESD array maybe designed. In step 910, it is established that there is a need for anESD network. In step 920, the engineers will define the reliabilityrequirement for a SEU using, e.g., characterizations from transmissionline pulse testing with energy ranges similar to those used in humanbody model (HBM) ESD qualification testing or cable discharge events(CDE). Then, input from the technology database file and ESD data 935 isused to define the ESD requirement in step 930. For example, for ESDprotection in military applications, an ESD network may be required thatprotects against a 1 MeV particle through the Van Allen belt, or protectagainst a 500-volt pulse on the input pad or 15,000 volts human bodymodel (HBM). Such ESD requirements that the circuit must be able towithstand can be further delineated by viewingwww.esda.org/standardlistings.html. In step 940, the circuit topology940 of the ESD network and if an array is used, the topology of thearray is designed. Using an SEU tool 955 that determines the probabilityof failure using, e.g., a Monte Carlo alpha particle or a cosmic raysimulator, the layout design of the unit cell is defined in step 950. Instep 960, the probability requirement of failure is evaluated. With theunit cell thus defined, the failure probability evaluated for aparticular circuit, the process completes at step 990.

It will be appreciated that variations of some elements are possible toadapt the invention for specific conditions or functions. The conceptsof the present invention can be further extended to a variety of otherapplications that are clearly within the scope of this invention. Havingthus described the present invention with respect to preferredembodiments as implemented, it will be apparent to those skilled in theart that many modifications and enhancements are possible to the presentinvention without departing from the basic concepts as described in thepreferred embodiment of the present invention. Therefore, what isintended to be protected by way of letters patent should be limited onlyby the scope of the following claims.

1. A fault tolerant electrostatic discharge network, comprising: a firsttrigger element; a first array of unit cells initialized by said firsttrigger element, each unit cell of said first array comprising aplurality of transistors, an electrical sum of all unit cells of saidfirst array being electrically equivalent to a first single voltageclamp element connected to said first trigger circuit element; a secondtrigger element, said first trigger element coupled in series with saidsecond trigger element; and a second array of unit cells initialized bysaid second trigger element, each unit cell of said second arraycomprising a plurality of transistors, an electrical sum of all unitcells of said second array being electrically equivalent to a secondsingle voltage clamp, said second array coupled in series with saidfirst array.
 2. The fault tolerant electrostatic discharge network ofclaim 1, wherein every unit cell of said first array is different. 3.The fault tolerant electrostatic discharge network of claim 1, whereinevery unit cell of said first array of unit cells is the same.
 4. Thefault tolerant electrostatic discharge network of claim 1, wherein atleast one unit cell of said first array is different from at least oneother unit cell of said first array.
 5. The fault tolerant electrostaticdischarge network of claim 1, wherein each unit cell of said secondarray is different.
 6. The fault tolerant electrostatic dischargenetwork of claim 1, wherein each unit cell of said second array of unitcells is the same.
 7. The fault tolerant electrostatic discharge networkof claim 1, wherein at least one unit cell of said second array isdifferent from at least one other unit cell of said second array.
 8. Thefault tolerant electrostatic discharge network of claim 1, wherein everyunit cell of said first array and every unit cell of said second arrayof unit cells are different.
 9. The fault tolerant electrostaticdischarge network of claim 1, wherein every unit cell of said firstarray and every unit cell of said second array is the same unit.
 10. Thefault tolerant electrostatic discharge network of claim 1, wherein atleast one unit cell of said first array or of said second array isdifferent from at least one other unit cell of said first array or saidsecond array.
 11. The fault tolerant electrostatic discharge network ofclaim 1, wherein the said unit cells of said first array and said unitcells of said second array are separated by a charge barrier.
 12. Thefault tolerant electrostatic discharge network of claim 11 wherein thecharge barrier is a trench.
 13. The fault tolerant electrostaticdischarge network of claim 11 wherein the charge barrier is a set ofN-wells. 14 The fault tolerant electrostatic discharge network of claim11 wherein the charge barrier is a substrate contact.
 15. A method,comprising: (a) defining a reliability requirement of an integratedcircuit for a single event upset; (b) defining an electrostaticdischarge requirement using a technology database file and electrostaticdischarge data; (c) defining circuit topology having a redundantelectrostatic discharge element in series with a voltage clampingelement of the electrostatic discharge protection network to be appliedbetween a first voltage and a second voltage in the integrated circuit;(d) defining a unit cell to comprise the redundant electrostaticdischarge element using a single event upset simulation tool; (e)evaluating the probability of failure of the electrostatic dischargeprotection network; and (f) adding a design of said electrostaticdischarge protection network to a design of said integrated circuit. 16.The method of claim 15, further including: between steps (e) and (f),repeating steps (b) through (e) until said design of said electrostaticdischarge protection network meets said reliability of said integratedcircuit.